Apple's iPhone 15 Series Unveiled Apple's iPhone 15 and iPhone 15 Pro series have been officially launched, with the A17 Pro chip, a major highlight, leading the way this year.

The A17 Pro is manufactured using TSMC's latest 3nm process (N3), boasting a whopping 190 billion transistors. This marks the first time TSMC's 3nm process has been applied to top-tier chips. The 3nm process offers a 70% increase in transistor density compared to the 5nm process, allowing for a 15% speed boost at the same power consumption or a 30% power reduction at the same speed.

According to TSMC's data, its 3nm node can be divided into N3B, N3E, N3P, N3X, etc., with N3B essentially being N3. The reason for this segmentation is TSMC's optimization across different technical benchmarks.

While the A17 Pro debuted with the N3 process, its journey to creation wasn't smooth. There were rumors that Apple initially planned to introduce this node with the A16, meaning the N3 debut was delayed by a year. Furthermore, there were whispers that Apple considered abandoning the N3 due to its subpar energy efficiency. TSMC also reportedly contemplated dropping it, presumably due to a lack of core customers. Indeed, companies like AMD, NVIDIA, and MediaTek seemed to have shifted their focus to N3E.

Adding to the intrigue, just before the new iPhone's release, a "betting" agreement between TSMC and Apple pushed TSMC into the spotlight.

The agreement stipulates that TSMC's 3nm will be exclusively for Apple for the next year. If any defective chips are produced, TSMC, breaking from industry norms, will absorb the costs instead of passing them onto Apple. This alone could save Apple billions of dollars in additional expenses.

This concession by TSMC is unusual, as it grants Apple exclusive access to TSMC's cutting-edge 3nm process for an entire year, enhancing Apple's competitive edge. So, why would TSMC make such a significant concession for Apple?

TSMC's history of manufacturing chips for Apple dates back to 2014 when Apple handed over the production of its self-developed A8 chip for the iPhone 6 to TSMC.

At that time, Apple also had Samsung manufacturing its chips. However, due to various reasons, including competition in the smartphone market and supply chain security concerns, Apple increasingly entrusted chip production to TSMC. Now, all of Apple's chips are produced by TSMC, making Apple TSMC's largest customer.

In June of this year, Apple, while launching its Vision Pro headset, also released two high-performance chips, the M2 Max and M2 Ultra, manufactured using TSMC's enhanced 5nm process. The earlier M1 series chips were also processed by TSMC using the standard 5nm process.

Over the past decade, the relationship between the two companies has deepened, expanding from mobile devices to cutting-edge XR devices, making their partnership almost inseparable.

01 The "Defective Chips" and the $4 Billion Dilemma

TSMC's unprecedented move to absorb the costs of defective chips for Apple took the industry by surprise. Some speculate that TSMC is in a tight spot with Apple: failing to sign this agreement might mean losing orders from a client that accounts for a quarter of TSMC's revenue. No other client places as substantial orders for top-tier chips as Apple does. With the agreement in place, the A17 Pro chip could become a hot potato for TSMC.

The core issue here is the semiconductor industry's fundamental concept of yield rate, which refers to the percentage of chips on a wafer that function correctly. A wafer can produce hundreds of identical chips, which are then sliced and packaged into electronic products.

Traditionally, the cost of defective chips on the wafer is borne by the client, not the manufacturer. However, not all defective chips are entirely non-functional. Some might not achieve 100% of their design performance but can still be used in lower-end products by reducing their operating frequency, allowing the client to recoup some losses.

Typically, when a semiconductor manufacturing process matures, the yield rate can exceed 99%. Rumors suggest that the yield rate for the A17 Pro chips TSMC produced for Apple's iPhone 15 is quite low, only reaching 70-80%. This means TSMC might have to cover the costs for 20%-30% of defective chips. A rough estimate suggests that, given the cost of each 3nm wafer is around $30,000 and considering a conservative 20% defect rate, TSMC could incur additional expenses of $3.6 billion (equivalent to 26 billion yuan) over a year. This amount represents 10.6% of TSMC's 2022 profit of $34.1 billion.

If these calculations reflect reality, the only variable TSMC can control to reverse this significant loss is the yield rate.

02 Yield Rate Challenges: The Bell Labs Case

Yield rate not only determines a company's profitability but also dictates the pace at which the semiconductor industry progresses, even influencing whether a chip can be invented.

In the 1950s, Bell Labs was the most likely candidate to invent the chip. They had the resources, talent, and almost all the foundational technologies needed. However, they missed out on this historic invention, leaving it to then lesser-known companies like Texas Instruments and Fairchild Semiconductor.

The culprit? Yield rate.

Bell Labs' R&D head at the time believed that integrating many transistors would result in a product yield that was the product of the yield of each transistor. This meant that as the number of transistors on a chip increased, the overall yield would plummet, making chip production unprofitable.

However, this wasn't entirely accurate. Early chip yield rates were primarily affected by dust in the air , which could cause defects when settling on the wafer surface. While Morton assumed dust was evenly distributed, in reality, some areas might remain dust-free, achieving a 100% yield. If we liken dust particles to arrows and the silicon wafer to a target, with transistors as the bullseye, smaller targets have a lower probability of being "hit" by dust. A single dust particle might damage multiple transistors, but if they belong to one chip, only that chip is affected, leaving others intact. Thus, the chip yield wasn't as dismal as Morton predicted.

03 Protecting the Delicate Silicon Wafer

Contrary to Morton's meticulous reasoning, pioneering companies like Texas Instruments and Fairchild Semiconductor relentlessly explored ways to improve chip yield rates.

Initially, manufacturers transformed chip production facilities into ultra-clean rooms, ensuring they were over a thousand times cleaner than hospital operating rooms. Everyone entering these rooms had to wear protective suits, colloquially known as "bunny suits," from head to toe to prevent contaminants like hair and sweat from affecting the delicate silicon wafers.

Today's advanced manufacturing facilities are almost entirely automated, with robots and mechanical arms performing operations, minimizing human intervention.

One of the most authoritative voices on yield rate is TSMC's founder, Morris Chang. Early in his career at Texas Instruments, he was responsible for semiconductor manufacturing. Under his leadership, the yield rate for transistors manufactured for IBM increased from 2%-3% to over 20%, surpassing IBM's in-house production. Chang later recalled that this achievement earned him a sponsored Ph.D. study at Stanford University. Addressing the yield rate issue was undoubtedly one of his significant accomplishments at Texas Instruments.

Yield rate also dictates the pace of Moore's Law. If circuit designers make transistors smaller than Moore's Law predicts, wafer processing becomes challenging, impacting yield rates, escalating costs, and potentially slowing down chip advancements.

04 TSMC's Battle for Survival

Two months ago, reports suggested TSMC's 3nm process had a yield rate of just 55%. The latest figures indicate 70-80%, marking significant progress. If TSMC can further increase this to 90% or even 95% in the coming months, the cost implications of defective chips will drastically reduce.

Assuming a yield rate of 95%, TSMC's additional costs would drop from $3.6 billion to $900 million. If the yield rate hits 98%, the extra costs would further shrink to $360 million.

In such a scenario, TSMC's savings from improved yield rates, amounting to over $3 billion, would transform from a vulnerability into an asset.

While improving yield rates and profitability aligns with standard business logic, it doesn't entirely explain TSMC's decision to absorb the costs of defective chips. One must consider the broader industry perspective.

A significant signal came last year when Samsung announced the mass production of chips based on its 3nm GAA process, a full year ahead of TSMC's 3nm FinFET process.